An integrated circuit memory may be formed of an assembly of memory elements, or memory cells, which may be arranged in an array. The data writing into and reading from memory cells are performed by means of dedicated logic circuits. A power supply generally provides the power necessary to the proper operation of the memory cell components and of the logic circuit. The memory power supply is generally obtained by one or several rails connected to all the memory cells and transmitting a power supply voltage. A memory is called volatile in the case where the data stored in the memory cells risk being lost when the memory power supply voltage falls below a minimum threshold.
FIG. 1 shows an embodiment of a volatile memory cell 5 of a volatile memory of static random access memory type (SRAM). Memory cell 5 comprises six metal-oxide gate field-effect transistors, also called MOS transistors. Memory cell 5 belongs to a memory plane where the memory cells are distributed in rows and in columns.
Memory cell 5 comprises inverters INVL, INVR connected in antiparallel. Inverters INVL, INVR are connected between a source of a high voltage VDD and a source of a low voltage, generally ground GND. In the following description, the ground voltage is selected to be equal to 0 V. Inverter INVL comprises a P-type MOS transistor PUL having its source connected to voltage source VDD and having its drain connected to a node IL corresponding to the input of inverter INVR. Inverter INVL comprises an N-type MOS transistor PDL having its source connected to ground GND and having its drain connected to node IL. Inverter INVR comprises a P-type MOS transistor PUR having its source connected to the source of voltage VDD and having its drain connected to a node IR corresponding to the input of inverter INVL. Inverter INVR comprise an N-type MOS transistor PDR having its source connected to ground GND and having its drain connected to node IR. The gates of transistors PUL and PDL are connected to node IR and the gates of transistors PUR and PDR are connected to node IL.
Nodes IL and IR are connected to bit lines BLT and BLF via switches PGL and PGR controlled by a row selection signal transmitted by a word line WL. Switch PGL may be an N-type MOS transistor having its gate connected to word line WL and having its other conduction terminals respectively connected to bit line BLT and to node IL. Similarly, switch PGR may be an N-type MOS transistor having its gate connected to word line WL and having its other conduction terminals respectively connected to node IR and to bit line BLF. Word line WL extends over the memory row comprising memory cell 5 and is connected to each memory cell in the row. Bit lines BLT and BLF extend on the memory column to which memory cell 5 belongs and are connected to each memory cell in the column.
In the following description, a bit or word line is said to be in the low state when the voltage on this line is at a low level, for example, at ground voltage GND, and a bit or word line is said to be in the high state when the voltage on this line is at a high level, for example, approximately equal to power supply voltage VDD. However, the high and low levels may be different for each word and bit line.
Memory cell 5 enables to store a binary datum or bit “0” or “1”. As an example, the storage of datum “1” corresponds to the case where the voltage at node IL is in the high state and the voltage at node IR is in the low state and the storage of datum “0” corresponds to the case where the voltage at node IL is in the low state and the voltage at node IR is in the high state.
For certain applications, the consumption of the integrated circuit comprising a volatile memory is a critical factor. This may concern medical applications or wireless applications which require a low consumption. As an example, the integrated circuit may be provided on medical implants, portable electronic elements, or a sensor network. It is, for example, an integrated circuit equipping the cell phone, the integrated circuit being powered by the phone battery.
A reduction of the memory consumption may be obtained by decreasing the memory power supply voltage. However, the decrease of the power supply voltage may cause read errors in an operation of reading of the datum stored in memory cell 5.
Indeed, in an operation of reading of the datum stored in a memory cell, word line WL associated with the selected memory cell is set to the high state and the word lines of all the other memory rows are set to the low state. Switches PGL and PGR of the selected memory cell 5 are thus off. Bit lines BLT and BLF are left floating. According to the datum stored in the memory cell, the voltage of one of bit lines BLT, BLF rises and the voltage of the other bit line BLT, BLF decreases. However, even if switches PGL and PGR of all the other memory cells of the column are on, leakage currents may flow for these memory cells through some of switches PGL and PGR. With the decrease of power supply voltage VDD, the total leakage current corresponding to the sum of the leakage currents of the unselected memory cells of the column may cause incorrect variations of the voltages of bit lines BLT and BLF and thus read errors. It is then necessary to decrease the number of memory cells per column.
FIG. 2 shows an embodiment of a memory cell 10 such as that described in publication “A large σVTH/VDD tolerant Zigzag 8T SRAM with Area-Efficient decoupled differential sensing and fast write-back scheme” by Jui-Jen Wu, Yen-Huei Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, and Hiroyuki Yamauchi (IEEE Journal of Solid-State Circuits, Vol. 46, No 4, April 2011).
As compared with cell 5 shown in FIG. 1, memory cell 10 further comprises two read bit lines RBLT and RBLF, a read word line RWL, and two N-type MOS transistors, RPDL and RPDR, dedicated to read operations. The gate of transistor RPDL is connected to node IL. One of the conduction terminals of transistor RPDL is connected to read bit line RBLT and the other conduction terminal of transistor RPDL is connected to read word line RWL. The gate of transistor RPDR is connected to node IR. One of the conduction terminals of transistor RPDR is connected to read bit line RBLF and the other conduction terminal of transistor RPDR is connected to read word line RWL. Word line WL and bit lines BLT and BLF are dedicated to write operations.
In a write operation or a retention operation (between read and/or write operation), read bit lines RBLT and RBLF are set to VDD.
In a read operation, read bit lines RBLT and RBLF are left floating and read word line RWL of the selected memory cell 10 is set to the low state while the word lines RWL associated with the other memory rows are maintained in the high state. When datum ‘1’ is stored in memory cell 5, only transistor RPDR is conductive. The voltage of bit line RBLF decreases. Transistor RPDL is off and bit line RBLT remains in the high state. Voltage difference Vdiff between bit lines RBLT and RBLF can then be detected. The time for which read word line RWL is set to the low state is sufficiently short for voltage Vdiff to remain smaller than the threshold voltage of transistors RPDL and RPDR. For the other memory cells of the column, the gate-source voltage of transistors RPDL and RPDR is at most equal to Vdiff. These transistors thus remain off. Further, the drain-source voltage of transistors RPDL and RPDR of the unselected memory cells of the column is at most equal to Vdiff so that the leakage currents remain low as compared with those obtained for memory cell 5. Read errors are thus decreased even if the number of memory cells per column is high.
However, memory cell 10 shown in FIG. 2 has several disadvantages.
FIG. 3 illustrates disadvantages of a memory 15 comprising memory cells 10, two memory cells Cell1 and Cell2 being shown.
The consumption of memory 15 is increased with the appearing of parasitic currents during write operations. As an example, an operation of writing of a datum into memory cell Cell1 while no datum is to be written into memory Cell2 is considered. To achieve this, word line WL is set to the high state. One of bit lines BLT or BLF of memory cell Cell1 is set to the high state and the other bit line BLT or BLF is set to the low state according to the datum to be written into memory cell Cell1. Bit lines BLT and BLF associated with memory cell Cell2 are both left floating in the high state. Since switches PGL and PGR of memory cell Cell2 are on and one of transistors PDL or PDR is on, a parasitic current flows from one of bit lines BLT or BLF associated with memory cell Cell2 to ground GND.
The consumption of memory 15 is further increased by the appearing of parasitic currents in read operations. As an example, an operation of reading of the datum stored in memory cell Cell1 while no datum is to be read from memory Cell2 is considered. In a read operation, word line RWL is set to the low state. Bit lines RBLT and RBLF associated with memory cell Cell1 are both left floating in the high state. According to the datum stored in memory cell Cell1, the voltage of one of the two bit lines RBLT or RBLF decreases. Bit lines RBLT and RBLF associated with memory cell Cell2 may be left floating in the high state. Since one of transistors RPDL or RPDR of memory cell Cell2 is on, a parasitic current thus flows between one of bit lines RBLT and RBLF associated with memory cell Cell2 and read line RWL.
A memory cell overcoming all or part of the previously-described disadvantages is thus needed.